Performance and Low Power Driven VLSI Standard Cell Placement using Tabu Search

We engineer a well-known optimization technique namely Tabu Search (TS) [1] for the performance and low power driven VLSI standard cell placement problem [2], [3]. The above problem is of multiobjective nature since three possibly conflicting objectives are considered to be optimized subject to the constraint of layout width. These objectives are power dissipation, timing performance, and interconnect wire length. It is well known that optimizing cell placement for even a single objective namely total wire length a hard problem to solve. Due to imprecise nature of objective values, fuzzy logic is incorporated in the design of aggregating function. The above technique is applied to the placement of ISCAS-89 benchmark circuits and the results are compared with Adaptive-bias Simulated Evolution (SimE) approach reported in [4]. The comparison shows a significant improvement over the SimE approach.